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CONFERENCE PUBLICATIONS
| Published/Accepted for Publication |
| Disclaimer: The following publications are covered by copyright. Permission to make digital/hard copy of all or part of the following papers, technical reports, and presentations for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage. To copy oth erwise, to republish, to post on servers, or to redistribute to lists requires prior specific permission. |
| 2022 |
| AV Lakshmy, Chester Rebeiro, Swarup Bhunia, “FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs”, 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, January 17 - 20, 2022. |
| 2021 |
| Kshitij Raj, Arrush Hegde, Atul Prasad Deb Nath, Swarup Bhunia, Sandip Ray, “SSEL: An Extensible Specification Language for SoC Security”, Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Shanghai, China, December 16 - 18, 2021. |
| Naren Vikram Raj Masna, Rohan Reddy Kalavakonda, Reiner Dizon, Swarup Bhunia, “Smart and Connected Mask for Protection beyond the Pandemic”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Lansing, MI, USA, August 9 - 11, 2021. |
| Shuo Yang, Prabuddha Chakraborty, Swarup Bhunia, “Side-channel Analysis for Hardware Trojan Detection using Machine Learning”, IEEE International Test Conference India (ITC India), Bangalore, India, July 18 - 20, 2021. |
| Sandip Ray, Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia, “The Curious Case of Trusted IC Provisioning in Untrusted Testing Facilities”, Great Lakes Symposium on VLSI (GLSVLSI), Virtual Conference and Exhibition, June 22 - 25, 2021. |
| Abdulrahman Alaql, Xinmu Wang, Md Moshiur Rahman, Swarup Bhunia, “SOMA: Security evaluation of obfuscation methods via attack sequencing”, 22nd International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, April 7 - 9, 2021. |
| Shuo Yang, Prabuddha Chakraborty, Patanjali SLPSK, Swarup Bhunia, “Trusted Electronic Systems with Untrusted COTS”, 22st International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, April 7 - 9, 2021. |
| Sandip Ray, Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia, “CASTLE: Architecting Assured System-on-Chip Firmware Integrity”, Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, February 1 - 5, 2021. |
| 2020 |
| Tamzidul Hoque, Patanjali SLPSK, Swarup Bhunia, “Trust issues in COTS: The challenges and emerging solution”, Great Lakes Symposium on VLSI (GLSVLSI), Virtual Event, China, September 7 - 9, 2020. |
| Prabuddha Chakraborty, Robert Parker, Tamzidul Hoque, Jonathan Cruz, Swarup Bhunia, “P2C2: Peer-to-Peer Car Charging”, 91st IEEE Vehicular Technology Conference (VTC), Antwerp, Belgium, May 25 - 28, 2020. |
| Ahish Shylendra, Priyesh Shukla, Swarup Bhunia, Amit Ranjan Trivedi, “Fault attack detection in AES by monitoring power side-channel statistics”, 21st International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, March 25 - 26, 2020. |
| Milind Srivastava, Patanjali Slpsk, Indrani Roy, Chester Rebeiro, Aritra Hazra, Swarup Bhunia, “SOLOMON: An automated framework for detecting fault attack vulnerabilities in hardware”, Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, November 9 - 17, 2020. |
| 2019 |
| Abdulrahman Alaql, Domenic Forte, Swarup Bhunia, “Sweep to the secret: A constant propagation attack on logic locking”, Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Xi'an, China, November 16 - 17, 2019. |
| Domenic Forte, Swarup Bhunia, Ramesh Karri, Jim Plusquellic, Mark Tehranipoor, “IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future”, IEEE International Test Conference (ITC), Washington, DC, USA, November 9 - 15, 2019. |
| Jungmin Park, Seongjoon Cho, Taejin Lim, Swarup Bhunia, Mark Tehranipoor, “SCR-QRNG: Side-channel resistant design using quantum random number generator”, 38th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, USA, November 4 - 7, 2019. |
| Nicholas Olexa, Rashmi Jha, Soumyajit Mandal, Swarup Bhunia, “ReRAM-Based Intrinsically Secure Memory: A Feasibility Analysis”, IEEE National Aerospace and Electronics Conference (NAECON), Dayton, OH, USA, July 15 - 19, 2019. |
| Swarup Bhunia, “Innovations in IoT for a Safe, Secure, and Sustainable Future”, 29th Proceedings of the 2019 on Great Lakes Symposium on VLSI, Tysons Corner, VA, USA, May 9 - 11, 2019. |
| Swarup Bhunia, “Innovations in IoT for a Safe, Secure, and Sustainable Future”, 29th Proceedings of the 2019 on Great Lakes Symposium on VLSI, Tysons Corner, VA, USA, May 9 - 11, 2019. |
| Prabuddha Chakraborty, Jonathan Cruz, and Swarup Bhunia, “SURF: Joint Structural Functional Attack on Logic Locking”, 12th IEEE Hardware Oriented Security and Trust (HOST), McLean, VA, USA, May 6 - 10, 2019. |
| Hassan Salmani, Tamzidul Hoque, Swarup Bhunia, Muhammad Yasin, Jeyavijayan JV Rajendran, Naghmeh Karimi, “Special session: countering IP security threats in supply chain”, 37th 2019 IEEE 37th VLSI Test Symposium (VTS), Monterey, CA, USA, April 23 - 25, 2019. |
| Abdulrahman Alaql, Tamzidul Hoque, Domenic Forte, Swarup Bhunia, “Quality Obfuscation for Reliable and Adaptive Hardware IP Protection”, 37th IEEE VLSI Test Symposium (VTS), Monterey, CA, USA, April 23 - 25, 2019. |
| Swarup Bhunia, “New Frontiers in Hardware Security in the IoT Regime”, 2019 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, April 14 - 17, 2019. |
| Shuo Yang, Abdulrahman Alaql, Tamzidul Hoque, Swarup Bhunia, “Runtime Integrity Verification in Cyber-physical Systems using Side-Channel Fingerprint”, 37th 2019 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, USA, January 11 - 13, 2019. |
| Atul Prasad Debnath, Srivalli Boddupalli, Swarup Bhunia, and Sandip Ray, “ARK: Architecture for Security Resiliency in SoC Designs with NetworK-on-Chip (NoC) Fabrics”, to appear in GOMACTech-19 Conference, Albuquerque, NM, USA, March 25 - 28, 2019. |
| 2018 |
| Prabuddha Chakraborty, Jonathan Cruz, and Swarup Bhunia, “SAIL: Machine Learning Guided Structural Analysis Attack on Hardware Obfuscation”, to appear in 3rd Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Hong Kong, Dec 17 - 18, 2018. |
| Tamzidul Hoque, Jonathan Cruz, Prabuddha Chakraborty, and Swarup Bhunia, “Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify”, to appear in 49th International Test Conference (ITC), Phoenix, AZ, USA, Oct 26 - Nov 1, 2018. |
| Haoting Shen, Mark Tehranipoor, and Swarup Bhunia, “Tampering, Snooping, and Electromagnetic Attack Proof Coating on Printed Circuit Boards”, to appear in 44th International Symposium for Testing and Failure Analysis (ISTFA), Phoenix, AZ, USA, Oct 26 - Nov 1, 2018. |
| Kai Yang, Jungmin Park, Mark Tehranipoor, and Swarup Bhunia, “Robust Timing Attack Countermeasure on Virtual Hardware”, to appear in IEEE Computer Society Annyal Symposium on VLSI (ISVLSI), Hong Kong SAR, China, July 9-11, 2018. |
| Atul Prasad Debnath, Swarup Bhunia, and Sandip Ray, “ArtiFact: Architecture and CAD Flow for Ef?cient Formal Veri?cation of SoC Security Policies”, to appear in IEEE Computer Society Annyal Symposium on VLSI (ISVLSI), Hong Kong SAR, China, July 9-11, 2018. |
| Ahish Shylendra, Swarup Bhunia, and Amit Ranjan Trivedi, “Intrinsic and Database-free Watermarking in ICs by Exploiting Process and Design Dependent Variability in Metal-Oxide-Metal Capacitances”, to appear in ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2018 [Poster Presentation]. |
| Mehrdad Ramezani, Angela Newsome, Swarup Bhunia, and Roozbeh Tabrizian, “Nanomechanical Identification Tag Technology For Traceability and Authentication Applications”, to appear in Hilton Head 2018 Solid-State Sensors, Actuators & Microsystems Workshop, Hilton Head, USA, June 3 - June 7, 2018 [Poster Presentation]. |
| Kai Yang, Jungmin Park, Mark Tehranipoor, and Swarup Bhunia, “Hardware Virtualization for Protection against Power Analysis Attack”, to appear in 11th IEEE Hardware Oriented Security and Trust (HOST), Washington DC, April 30 - May 4, 2018 [Poster Presentation]. |
| Tamzidul Hoque, Xinmu Wang, Abhishek Basak, Robert Karam, and Swarup Bhunia, “Hardware Trojan Attack in Embedded Memory”, to appear in IEEE VLSI Test Symposium (VTS), San Francisco, April 22 - 25, 2018. |
| Angela Newsome, Mehrdad Ramezani, Mayur Ghatge, Fengchao Zhang, Swarup Bhunia, and Roozbeh Tabrizian, “Multi-Mode Micromechanical Resonant Tags for Traceability and Authentication Applications”, to appear in 13th Annual IEEE Conference on Nano/Micro Engineered and Molecular Systems (NEMS), Singapore, April 22 - 26, 2018. |
| Jonathan Cruz, Yuanwen Huang, Prabhat Mishra and Swarup Bhunia, “An Automated Configurable Trojan Insertion Framework for Dynamic Trust Benchmarks”, to appear in 23rd Design Automation and Test in Europe (DATE) Conference, Dresden, Germany, March 19 - 23, 2018. |
| Atul Prasad Debnath, Sandip Ray, Abhishek Basak, and Swarup Bhunia, “System-on-Chip Security Architecture and CAD Framework”, 23rd Asia and South Pacific Design Automation Conference (ASPDAC), Korea, January 22 - 25, 2018. |
| 2017 |
| Fengchao Zhang, Naren Masna, Cheng Chen, Soumyajit Mandal, and Swarup Bhunia, “Authentication and Traceability of Food Products Through the Supply Chain Using NQR Spectroscopy”, to appear in IEEE BioCAS, FoodCAS Lecture session, Italy, October 2017. |
| Robert Karam, Tamzidul Hoque, Kevin Butler, and Swarup Bhunia, “Mixed-Granular Architectural Diversity for Device Security in the Internet of Things”, to appear in AsianHOST, 2017. |
| Jungmin Park, Massimiliano Corba, Antonio E. de la Serna, Richard L. Vigeant, Mark Tehranipoor, and Swarup Bhunia, ”ATAVE: a Framework for Automatic Timing Attack Vulnerability Evaluation“, to appear in IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017. [Abstract] |
| Kai Yang, Robert Karam, and Swarup Bhunia, “Interleaved Logic-in-Memory Architecture for Energy-Efficient Fine-Grained Data Processing”, to appear in IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017. [Abstract] |
Robert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor, and Swarup Bhunia,
“MUTARCH: Architectural Diversity for FPGA Device and IP Security”,
to appear in 22nd Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, January 16 - 19, 2017.
[Abstract]
[Full Text: PDF  ]
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Gustavo K. Contreras, Adib Nahiyan, Swarup Bhunia, Domenic Forte, Mark Tehranipoor,
“Security Vulnerability Analysis of Design-for-Test Exploits for Asset Protection in SoCs”,
to appear in 22nd Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, January 16 - 19, 2017.
[Abstract]
[Full Text: PDF ]
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| 2016 |
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Robert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor and Swarup Bhunia,
“Robust Bitstream Protection in FPGA-based Systems through Low-Overhead Obfuscation”,
to appear in International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, Nov 30 - Dec 2, 2016.
[Abstract]
[Full Text: PDF ]
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Yuanwen Huang, Swarup Bhunia, and Prabhat Mishra,
“MERS: Statistical Test Generation for Side-Channel Analysis based Trojan Detection”,
to appear in ACM Conference on Computer and Communications Security (CCS), Vienna, Austria, October 24 - 28, 2016.
[Abstract]
[Full Text: PDF ]
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Sumaiya Shomaji, Abhishek Basak, Soumyajit Mandal, Swarup Bhunia,
“A Wearable Carotid Ultrasound Assembly for Early Detection of Cardiovascular Diseases”,
to appear in IEEE-NIH Special Topics Conference on Healthcare Innovations and Point-of-Care Technologies (HI-POCT), Cancun, Mexico, Nov 9 - 11, 2016.
[Abstract]
[Full Text: PDF ]
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Robert Karam, Steve Majerus, Dennis Bourbeau, Margot Damaser, and Swarup Bhunia,
“Ultralow-Power Data Compression for Implantable Bladder Pressure Monitor: Algorithm and Hardware Implementation”,
to appear in IEEE Biomedical Circuits & Systems Conference (BIOCAS), 2016. [Best Paper Award]
[Abstract]
[Full Text: PDF ]
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Zimu Guo, Bicky Shakya, Haoting Shen, Swarup Bhunia, Navid Asadizanjani, Domenic Forte, Mark Tehranipoor,
“A New Methodology to Protect PCBs from Non-destructive Reverse Engineering”,
to appear in International Symposium for Testing and Failure Analysis (ISTFA), Texas, USA, November 6 - 10, 2016.
[Abstract]
[Full Text: PDF ]
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Dylan Ismari, Charles Lamech, Swarup Bhunia, Fareena Saqib, and James Plusquellic,
“On Detecting Delay Anomalies Introduced by Hardware Trojans”,
to appear in 35th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016.
[Abstract]
[Full Text: PDF ]
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Robert Karam, Swarup Bhunia, Steve Majerus, Steven Brose, Margot S. Damaser, Dennis Bourbeau,
“Real-time, Autonomous Bladder Event Classification and Closed-Loop Control from Single-Channel Pressure Data”,
to appear in 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2016.
[Abstract]
[Full Text: PDF ]
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Sumaiya Shomaji, Abhishek Basak, Soumyajit Mandal, Swarup Bhunia,
“A Wearable Carotid Ultrasound Assembly for Early Detection of Cardiovascular Diseases”,
to appear in 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2016.
[Abstract]
[Full Text: PDF ]
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| Robert Karam, Steve Majerus, Swarup Bhunia, Steven Brose, Margot S. Damaser, and Dennis Bourbeau, “Autonomous closed-loop genital nerve stimulation identifies and inhibits hyper-reflexic bladder contractions”, to appear in Engineering and Urology Society (EUS) 31st Annual Meeting, 2016. |
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Abhishek Basak, Swarup Bhunia, and Sandip Ray,
“Exploiting Design-for-Debug for Flexible SoC Security Architecture”,
to appear in Design Automation Conference (DAC), 2016.
[Abstract]
[Full Text: PDF ]
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Steven Paley, Tamzidul Hoque, and Swarup Bhunia,
“Active Protection against PCB Physical Tampering”,
to appear in 17th International Symposium on Quality Electronic Design (ISQED), 2016.
[Abstract]
[Full Text: PDF ]
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Fengchao Zhang, James Plusquellic, and Swarup Bhunia,
“Current based PUF Exploiting Random Variations in SRAM Cells”,
to appear in Design Automation and Test in Europe (DATE), 2016.
[Abstract]
[Full Text: PDF ]
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| Wenchao Qian, Christopher Babecki, Robert Karam, and Swarup Bhunia, “ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric”, to appear in 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), [Accepted as a poster presentation], 2016. [Abstract] |
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Andrew Hennessy, Yu Zheng, and Swarup Bhunia,
“JTAG-Based Robust PCB
Authentication for Protection against Counterfeiting Attacks”,
to appear in 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 2016.
[Abstract]
[Full Text: PDF ]
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| 2015 |
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Abhishek Basak, Sandip Ray, and Swarup Bhunia,
“A Flexible Architecture for Systematic Implementation of SoC Security Policies”,
to appear in 34th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015.
[Abstract]
[Full Text: PDF ]
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Abhishek Basak, Fengchao Zhang, and Swarup Bhunia,
“PiRA: IC Authentication Utilizing Intrinsic Variations in Pin Resistance”,
to appear in International Test Conference (ITC), 2015.
[Abstract]
[Full Text: PDF ]
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Jae-Won Jang, Jongsun Park, Swaroop Ghosh, and Swarup Bhunia,
“Self-Correcting STTRAM under Magnetic Field Attacks”,
Design Automation Conference (DAC), 2015.
[Abstract]
[Full Text: PDF ]
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Fengchao Zhang, Andrew Henessy, and Swarup Bhunia,
“Robust Counterfeit PCB Detection Exploiting Intrinsic Trace Impedance Variations”,
33rd IEEE VLSI Test Symposium (VTS), 2015.
[Abstract]
[Full Text: PDF ]
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| Irene Makovey, Robert Karam, Steve Majerus, Dennis Bourbeau, Hui Zhu, Swarup Bhunia, and Margot S. Damaser, “Event Detection Algorithm in Single Channel Bladder Pressure Recording 8221;, Engineering and Urology Society (EUS) 30th Annual Meeting, 2015. |
| 2014 |
Wenjie Che, Swarup Bhunia, and Jim Plusquellic,
“A Non-Volatile Memory based Physically Unclonable Function without Helper Data”,
IEEE International Conference on Computer Aided Design (ICCAD),
2014.
[Full Text: PDF  ]
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Yu Zheng, Abhishek Basak, and Swarup Bhunia,
“CACI: Dynamic Current Analysis towards Robust Recycled Chip Identification”,
DAC '14 Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference,
pp. 1-6, 2014.
[Abstract]
[Full Text: PDF ]
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Abhishek Basak, Yu Zheng, and Swarup Bhunia,
“Active Defense against Counterfeiting Attacks through Robust On-Chip Locks”,
VLSI Test Symposium (VTS), 2014 IEEE 32nd,
pp. 1-6, 2014.
[Abstract]
[Full Text: PDF ]
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Sanchita Mal-Sarkar, Aswin Krishna, Anandaroop Ghosh, Swarup Bhunia,
“Hardware Trojan Attacks in FPGA Devices: Threat Analysis and Effective Countermeasures”,
GLSVLSI '14 Proceedings of the 24th edition of the great lakes symposium on VLSI,
pp. 287-292, 2014.
[Abstract]
[Full Text: PDF ]
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Wenchao Qian, Robert Karam, and Swarup Bhunia,
“Trade-off between Energy and Quality of Service Through Dynamic Operand Truncation and Fusion”,
GLSVLSI '14 Proceedings of the 24th edition of the great lakes symposium on VLSI,
pp. 79-81, 2014.
[Abstract]
[Full Text: PDF ]
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| Vaishnavi Ranganathan, Tina He, Srihari Rajgopal, Mehran Mehregany, Philip X.-L. Feng, and Swarup Bhunia, “Analysis of Practical Scaling Limits in Nanoelectromechanical Switches”, The 9th Annual IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS), 2014. |
| 2013 |
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Tina He, Vaishnavi Ranganathan, Rui Yang, Srihari Rajgopal, Mary Anne Tupta, Mehran Mehregany, Swarup Bhunia, and Philip X.-L. Feng,
“Silicon Carbide (SiC) Nanoelectromechanical Switches and Logic Gates with Long Cycles and Robust Performance in Ambient Air and at High Temperature”,
Micro Electro Mechanical Systems (MEMS), 2013 IEEE 26th International Conference on,
pp. 516-519, 2013.
[Abstract]
[Full Text: PDF ]
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Yu Zheng, MaryamSadat Hashemian, and Swarup Bhunia,
“A Robust Physical Unclonable Function Retrofitted into Embedded SRAM Array”,
Design Automation Conference (DAC), 2013 50th ACM / EDAC / IEEE,
pp. 1-9, 2013.
[Abstract]
[Full Text: PDF ]
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Xinmu Wang, Wen Yueh, Debapriya Basu Roy, Saibal Mukhopadhyay, Debdeep Mukhopadhyay, and Swarup Bhunia,
“Role of Power Grid in Side Channel Attack and Power-Grid-Aware Secure Design”,
Design Automation Conference (DAC), 2013 50th ACM / EDAC / IEEE,
pp. 1-9, 2013.
[Abstract]
[Full Text: PDF ]
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Hadi Hajimiri, Prabhat Mishra, Swarup Bhunia, Branden Long, Yibo Li, and Rashmi Jha,
“Content-aware Encoding for Improving Energy Efficiency in Resistive Random Access Memory”,
Nanoscale Architectures (NANOARCH), 2013 IEEE/ACM International Symposium on,
pp. 76-81, 2013.
[Abstract]
[Full Text: PDF ]
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Vaishnavi Ranganathan, Tina He, Srihari Rajgopal, Mehran Mehregany, Philip X.-L. Feng, and Swarup Bhunia,
“Robust Nanomechanical Non-Volatile Memory for Computing at Extreme”,
Nanoscale Architectures (NANOARCH), 2013 IEEE/ACM International Symposium on,
pp. 44-45, 2013.
[Abstract]
[Full Text: PDF ]
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Tina He, Vaishnavi Ranganathan, Rui Yang, Srihari Rajgopal, Swarup Bhunia, Mehran Mehregany, and Philip X.-L. Feng,
“Time-Domain AC Measurement of SiC Nanoelectromechanical Switches toward High Speed Operations”,
Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS & EUROSENSORS XXVII), 2013 Transducers & Eurosensors XXVII: The 17th International Conference on,
pp. 669-672, 2013.
[Abstract]
[Full Text: PDF ]
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| Yibo Li, Wenbo Chen, Ammaarah El-Amin, Rashmi Jha, Swarup Bhunia, and Philip X.-L. Feng, “A Reconfigurable Sensing and Computing Platform for Artificial Electronic Skins”, MRS Spring Meeting (Symposium TT: Materials and Processes for Artificial Skin), 2013. |
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Yu Zheng, Aswin Raghav Krishna, and Swarup Bhunia,
“ScanPUF: Robust Ultralow Overhead PUF Using Scan Chain”,
Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific,
pp. 626-631, 2013.
[Abstract]
[Full Text: PDF ]
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| 2012 |
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Xinmu Wang, Tatini Mal-Sarkar, Aswin Krishna, Seetharam Narasimhan, and Swarup Bhunia,
“Software Exploitable Hardware Trojan Attacks in Embedded Processor”,
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2012 IEEE International Symposium on,
pp. 55-58, 2012.
[Student Paper Award]
[Abstract]
[Full Text: PDF ]
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Tina He, Rui Yang, Srihari Rajgopal, Swarup Bhunia, Mehran Mehregany, and Philip X.-L. Feng,
“Dual-gate silicon carbide (SiC) lateral nanoelectromechanical switches”,
Nano/Micro Engineered and Molecular Systems (NEMS), 2013 8th IEEE International Conference on,
pp. 554-557, 2013.
[Best Student Paper Award]
[Abstract]
[Full Text: PDF ]
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Abhishek Basak, Vaishnavi Ranganathan, and Swarup Bhunia,
“A Wearable Ultrasonic Assembly for Point-Of-Care Autonomous Diagnostics of Malignant Growth”,
Point-of-Care Healthcare Technologies (PHT), 2013 IEEE,
pp. 128-131, 2013.
[Best Student Paper Award]
[Abstract]
[Full Text: PDF ]
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Tina He, Rui Yang, Srihari Rajgopal, Mary Anne Tupta, Swarup Bhunia, Mehran Mehregany, and Philip X.-L. Feng,
“Robust Silicon Carbide (SiC) Nanoelectromechanical Switches with Long Cycles in Ambient and High Temperature Conditions”,
Micro Electro Mechanical Systems (MEMS), 2013 IEEE 26th International Conference on,
pp. 516-519, 2012.
[Abstract]
[Full Text: PDF ]
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Maryamsadat Hashemian and Swarup Bhunia,
“Ultralow-Power and Robust Embedded Memory for Bioimplantable Microsystems”,
VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on,
pp. 66-71, 2012.
[Abstract]
[Full Text: PDF ]
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Hadi Hajimiri, Prabhat Mishra, and Swarup Bhunia,
“Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures”,
VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on,
pp. 49-54, 2012.
[Abstract]
[Full Text: PDF ]
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Abhishek Basak, Vaishnavi Ranganathan, Seetharam Narasimhan, and Swarup Bhunia,
“Implantable Ultrasonic Dual Functional Assembly Detection and Treatment of Anomalous Growth”,
Engineering in Medicine and Biology Society (EMBC), 2012 Annual International Conference of the IEEE,
pp. 170-173, 2012.
[Best Student Paper Nomination]
[Abstract]
[Full Text: PDF ]
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Kamran Rahmani, Prabhat Mishra, and Swarup Bhunia,
“RMBC: Reconfigurable Memory-based Computing for Performance and Energy Improvement in Multicore Architectures”,
GLSVLSI '12 Proceedings of the great lakes symposium on VLSI,
pp. 287-290, 2012.
[Abstract]
[Full Text: PDF ]
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Xinmu Wang, Seetharam Narasimhan, and Swarup Bhunia,
“SCARE: Side-Channel Analysis based Reverse Engineering for Post-Silicon Validation”,
VLSI Design (VLSID), 2012 25th International Conference on,
pp. 304-309, 2012.
[Abstract]
[Full Text: PDF ]
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Anandaroop Ghosh, Somnath Paul, and Swarup Bhunia,
“Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks”,
VLSI Design (VLSID), 2012 25th International Conference on,
pp. 424-429, 2011.
[Abstract]
[Full Text: PDF ]
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Lei Wang, Somnath Paul, and Swarup Bhunia,
“Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory”,
25th International Conference on VLSI Design (VLSI), pp. 340-345, 2012. [Best Paper Award]
[Abstract]
[Full Text: PDF ] |
| 2011 |
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Rajat Subhra Chakraborty, Seetharam Narasimhan, and Swarup Bhunia,
“Embedded Software Security through Key-based Control Flow Obfuscation”,
international Conference on Security Aspects in Information Technology, High-Performance Computing and Networking (InfoSecHiComNet), 2011. [Abstract] [Full Text: PDF ] |
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Abhishek Basak, Seetharam Narasimhan, and Swarup Bhunia,
“Low Power Implantable Ultrasound Imager for Online Monitoring of Tumor Growth”,
33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2011. [Abstract] [Full Text: PDF ] |
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Aswin Raghav Krishna, Seetharam Narasimhan, Xinmu Wang, and Swarup Bhunia,
“MECCA: A Robust Low-Overhead PUF using Embedded Memory Array”,
Workshop on Cryptographic Hardware and Embedded Systems (CHES), 2011. [Abstract] [Full Text: PDF ] |
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Xinmu Wang, Seetharam Narasimhan, and Swarup Bhunia,
“NEMTronics: Symbiotic Integration of Nanoelectronic and Nanomechanical Devices for Energy-Efficient Adaptive Computing”,
7th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2011.
[Abstract] [Full Text: PDF ] |
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Seetharam Narasimhan, Xinmu Wang, Dongdong Du, Rajat Subhra Chakraborty, and Swarup Bhunia,
“TeSR: A Robust Temporal Self-Referencing Approach for Hardware Trojan Detection”, 4th IEEE
International Symposium on Hardware-Oriented Security and Trust (HOST), 2011. [Abstract] [Full Text: PDF ] |
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Abhishek Basak, Seetharam Narasimhan, and Swarup Bhunia,
“KiMS: Kids' Health Monitoring System at Day-Care Centers using Wearable Sensors and Vocabulary-based Accoustic
Signal Processing”, 13th IEEE International Conference on e-Health Networking,
Application & Services (Healthcom), 2011. [Abstract] [Full Text: PDF ] |
| Somnath Paul and Swarup Bhunia, “Memory Based Computing: Reshaping the fine-grained logic in a reconfigurable framework”, [Abstract] 18th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 283, 2011. [Abstract] |
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Xinmu Wang, Seetharam
Narasimhan, Aswin Krishna, Francis G. Wolff, Srihari Rajgopal,
Te-Hao Lee, Mehran Mehregany, and Swarup Bhunia, “High-Temperature
(>500°C) FPGA Using SiC Nano-Electro-Mechanical System Switches”, Design Automation and Test in Europe
(DATE), 2011. [Abstract] [Full Text: PDF ] |
|
Subho Chatterjee, Saibal Mukhopadhyay,
Mitchelle Rasquinha, Sudhakar Yalamanchili, Swarup Bhunia, and Somnath Paul, "Energy
Efficient Circuit-System Codesign For Spin Torque Transfer Random Access Memory (STTRAM)
In Submicron Technologies", Non-Volatile Memories Workshop (NVMW), 2011. [Abstract] [Full Text: PDF ] |
|
Subidh Ali, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty, and Swarup Bhunia,
“Multi-level Attack: an Emerging Threat Model for Cryptographic
Hardware”, Design Automation and Test in Europe
(DATE), 2011. [Abstract] [Full Text: PDF ] |
|
Keerthi Kunaparaju, Seetharam Narasimhan,
and Swarup Bhunia, “VaROT: Variation-Tolerant DSP Circuits Using Post-Silicon Truncation of Operand Width”,
IEEE International Conference on VLSI Design (VLSI), 2011. [Abstract] [Full Text: PDF |
| 2010 |
|
Dongdong Du,
Seetharam Narasimhan, Rajat Subhra Chakraborty and
Swarup Bhunia, “Self-Referencing: A Scalable Side-Channel
Approach for Hardware Trojan Detection”, Workshop on
Cryptographic Hardware and Embedded Systems (CHES), 2010. [Abstract] [Full Text: PDF ] |
|
Rajat Subhra Chakraborty and Swarup Bhunia,
“Embedded Software Security Through Key-based Obfuscation”, poster
presentation in Workshop on Cryptographic Hardware and
Embedded Systems (CHES), 2010. [Abstract] [Full Text: PDF |
|
Seetharam Narasimhan,
Xinmu Wang, and Swarup Bhunia, “Implantable Electronics:
Emerging Design Issues and An Ultra Light-weight Security Solution”,
IEEE Engineering in Medicine and Biology Society
Conference (EMBC), 2010. [Abstract] [Full Text: PDF |
|
Seetharam Narasimhan,
David McIntyre, Yu Zhou, Francis Wolff, Daniel Weyer, and
Swarup Bhunia, “A Supply-Demand Model Based Scalable Energy
Management System for Improved Energy Utilization Efficiency”, IEEE International Green Computing Conference (IGCC),
2010. [Abstract] [Full Text: PDF |
|
Somnath Paul
and Swarup Bhunia, “VAIL: Variation-Aware Issue Logic and
Performance Binning for Processor Yield and Profit Improvement”,
International Symposium on Low Power Electronics and
Design (ISLPED), 2010. [Abstract] [Full Text: PDF |
|
David McIntyre, Francis Wolff, Chris Papachristou, and Swarup
Bhunia, “Trustworthy Computing in a Multi-Core System Using
Distributed Scheduling”, IEEE International On-Line Testing
Symposium (IOLTS), 2010. [Abstract] [Full Text: PDF ] |
|
Chris Papachristou, Swarup Bhunia, and Francis Wolff,
“Network Calibration of Embedded Sensors”, IEEE National
Aerospace and Electronics Conference (NAECON), 2010. [Abstract] [Full Text: PDF ] |
|
Seetharam Narasimhan, Dongdong Du,
Rajat Subhra Chakraborty,
Somnath Paul, Francis Wolff, Chris Papachristou, Kaushik Roy and Swarup Bhunia,
“Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware
Trojan Detection Approach”, IEEE Symposium on Hardware Oriented
Security and Trust (HOST), 2010. [Best Paper Candidate] [Abstract] [Full Text: PDF |
|
Seetharam Narasimhan, Somnath Paul,
Rajat Subhra Chakraborty, Francis Wolff, Christos Papachristou,
Daniel Weyer, and Swarup Bhunia, "System Level Self-Healing for
Parametric Yield and Reliability Improvement under Power Bound,"
NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2010. [Abstract] [Full Text: PDF ] |
|
Rajat Subhra Chakraborty
and Swarup Bhunia, “RTL Hardware IP Protection Using
Key-Based Control and Data Flow Obfuscation”, 23rd
International Conference on VLSI Design, pp. 405-410, 2010.
[Abstract] [Full Text: PDF |
| 2009 |
|
Somnath Paul,
Subho Chatterjee, Saibal Mukhopadhyay and Swarup Bhunia,
“Nanoscale Reconfigurable Computing Using Non-Volatile 2-D STTRAM
Array”, 9th International Conference on Nanotechnology
(IEEE Nano), pp. 880-883, 2009. [Abstract] [Full Text: PDF ] |
|
Somnath Paul,
Subho Chatterjee, Saibal Mukhopadhyay and Swarup Bhunia, "A
Circuit-Software Co-Design Approach for Improving EDP in
Reconfigurable Frameworks," IEEE International Conference on
Computer Aided Design (ICCAD), pp. 109-112, 2009. [Abstract] [Full Text: PDF ] |
|
Somnath Paul,
Saibal Mukhopadhyay and Swarup Bhunia, "A Variation-Aware
Preferential Design Approach for Memory Based Reconfigurable
Computing," IEEE International Conference on Computer Aided
Design (ICCAD), pp. 180-183, 2009. [Abstract] [Full Text: PDF |
|
Rajat Subhra Chakraborty
and Swarup Bhunia, "Security through Obscurity: An Approach
for Protecting Register Transfer Level Hardware IP," IEEE
Hardware Oriented Security and Trust (HOST) Workshop, pp. 96-99,
2009. [Abstract] [Full Text: PDF ] |
|
David McIntyre, Francis Wolff, Chris Papachristou, Swarup Bhunia
and Dan Weyer, "Dynamic Evaluation of Hardware Trust," IEEE
Hardware Oriented Security and Trust (HOST) Workshop, pp.
108-111, 2009. [Abstract] [Full Text: PDF ] |
|
Rajat Subhra Chakraborty, Francis Wolff, Somnath
Paul, Christos Papachristou and Swarup Bhunia, "MERO: A Statistical
Approach for Hardware Trojan Detection", Workshop on Cryptographic
Hardware and Embedded Systems (CHES), 2009. [Appeared in the "Hot Topic Session: Hardware Trojans and Trusted ICs"]
[Abstract]
[ Full
Text: PDF ] |
|
Rajat Subhra Chakraborty
and Swarup Bhunia, "Security against Hardware Trojan through
a Novel Application of Design Obfuscation," IEEE International
Conference on Computer Aided Design (ICCAD), pp. 113-116, 2009. [Abstract] [Full Text: PDF ] |
|
Seetharam Narasimhan,
Hillel J. Chiel and Swarup Bhunia, “A Preferential Design
Approach for Energy-Efficient and Robust Implantable Neural Signal
Processing”, IEEE Engineering in Medicine and Biology Society
Conference (EMBC), pp. 6383-6386, 2009. [Best Student Paper
Finalist (one of 15)] [Abstract] [Full Text: PDF |
|
Te-Hao Lee, Kevin M. Speer, Xiaoan Fu, Swarup Bhunia,
and Mehran Mehregany, "Polycrystalline Silicon Carbide NEMS for
High-Temperature Logic," pp. 900-903, Transducers, 2009. [Abstract] [Full Text: PDF |
| 2008 |
|
Te-Hao Lee, Kevin M. Speer, Kenji Okino, Xiaoan Fu, Swarup
Bhunia, and Mehran Mehregany, “Polycrystalline-SiC
Nanoelectromechanical Switches for High-Temperature Switching and
Logic Applications”, IEEE Nanotechnology and Device Conference (NMDC),
2008. [Abstract] [Full Text: PDF |
|
Rajat Subhra Chakraborty
and Swarup Bhunia, “Hardware Protection Through Netlist-Level
Obfuscation”, IEEE International Conference on Computer Aided
Design (ICCAD), pp. 674-677, 2008. [Abstract] [Full Text: PDF |
|
Somnath Paul,
Saibal Mukhopadhyay, and Swarup Bhunia, “Hybrid CMOS-STTRAM
FPGA Design Optimization for Low Power and High Integration
Density”, IEEE International Conference on Computer Aided Design
(ICCAD), pp. 589-592, 2008. [Abstract] [Full Text: PDF |
|
Seetharam Narasimhan,
Miranda Cullins, Hillel Chiel, and Swarup Bhunia,
“Wavelet-Based Neural Pattern Analyzer for Behaviorally Significant
Burst Pattern Recognition”, IEEE Engineering in Medicine and
Biology Society Conference
(EMBC), pp. 38-41, 2008. [Abstract] [Full Text: PDF |
|
Rajat Subhra Chakraborty,
Somnath Paul, and Swarup Bhunia, “On-Demand
Transparency for Improving Hardware Trojan Detectability”, IEEE
Hardware Oriented Security and Trust (HOST) Workshop, pp. 48-50,
2008. [Abstract]
[Full
Text: PDF |
|
Seetharam Narasimhan,
Somnath Paul, and Swarup Bhunia, “Collective Computing
Based on Swarm Intelligence”, Design Automation Conference (DAC),
pp. 349-350, 2008. [as a WACI (Wild and Crazy Ideas) paper] [Abstract] [Full
Text: PDF |
|
Somnath Paul
and Swarup Bhunia, “Reconfigurable Computing Using Content
Addressable Memory for Improved Performance and Resource Usage”,
Design Automation Conference (DAC), pp. 786-791, 2008. [Abstract]
[Full
Text: PDF |
|
Matthew Holtz,
Seetharam Narasimhan, and Swarup Bhunia, “On-die CMOS
Voltage Droop Detection and Dynamic Compensation”, Great Lakes
Symposium on VLSI (GLSVLSI), pp. 35-40, 2008. [Abstract]
[Full
Text: PDF |
|
Rajat Subhra Chakraborty
and Swarup Bhunia, “Micropipeline-Based Asynchronous Design
Methodology for Robust System Design Using Nanoscale Crossbar”,
IEEE International Symposium on Quality Electronic Design (ISQED),
pp. 697-701, 2008. [Abstract]
[Full
Text: PDF |
|
Yu Zhou,
Somnath Paul, and Swarup Bhunia, “Towards Uniform
Temperature Distribution in SOI Circuits Using Carbon Nanotube Based
Thermal Interconnect”, IEEE International Symposium on Quality
Electronic Design (ISQED),
pp. 861-866, 2008. [Abstract]
[Full
Text: PDF |
|
Lawrence Leinweber
and Swarup Bhunia, “Fine-Grained Supply Gating Through
Hypergraph Partitioning and Shannon Decomposition for Active Power
Reduction”, Design Automation and Test in Europe (DATE), pp.
373-378, 2008. [Abstract]
[Full
Text: PDF |
|
Yu Zhou,
Somnath Paul and Swarup Bhunia, “Harvesting Wasted
Heat in a Microprocessor Using Thermo-Electric Generators: Modeling,
Analysis and Measurement”, Design Automation and Test in Europe
(DATE), pp. 98-103, 2008. [Abstract]
[Full
Text: PDF |
|
Francis Wolff, Christos Papachristou, Rajat Subhra
Chakraborty, and Swarup Bhunia, “Towards Trojan-Free
Trusted ICs: Problem Analysis and a Low-Overhead Detection Scheme”,
Design Automation and Test in Europe (DATE), pp. 1362-1365,
2008. [Abstract]
[Full
Text: PDF |
|
Rajat Subhra Chakraborty,
Somnath Paul, and Swarup Bhunia, "Analysis and Robust
Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits",
International Conference on VLSI Design, pp. 441-446, 2008. [Abstract]
[Full
Text: PDF |
|
Somnath Paul
and Swarup Bhunia, "MBARC: A Scalable Memory Based
Reconfigurable Computing Framework for Nanoscale Devices", Asia
and South Pacific Design Automation Conference (ASP-DAC), pp.
77-82, 2008. [Abstract]
[Full
Text: PDF |
| 2007 |
|
Seetharam Narasimhan,
Yu Zhou, Hillel J. Chiel, and Swarup Bhunia,
“Low-Power VLSI Architecture for Neural Data Compression Using
Vocabulary-based Approach”, IEEE Biomedical Circuits and Systems
Conference (BioCAS), 2007. [Abstract]
[Full
Text: PDF |
|
Somnath Paul
and Swarup Bhunia, “Memory Based Computation Using Embedded
Cache for Processor Yield and Reliability Improvement”,
International Conference on Computer Design (ICCD), pp. 341-346,
2007. [Abstract]
[Full
Text: PDF |
|
Somnath Paul,
Siva Krishnamurthy, Hamid Mahmoodi, and Swarup Bhunia,
“Low-Overhead Design Technique for Calibration of Maximum Frequency
at Multiple Operating Points”, IEEE International Conference on
Computer Aided Design (ICCAD), pp. 401-404, 2007. Abstract]
[Full
Text: PDF |
|
Yu Zhou,
Shijo Thekkel, and Swarup Bhunia, “Low power FPGA Design
Using Hybrid CMOS-NEMS Approach”, International Symposium on Low
Power Electronics and Design (ISLPED), pp. 14-19, 2007. [Abstract]
[Full
Text: PDF |
|
Somnath Paul,
Rajat Chakraborty, and Swarup Bhunia, “Defect-Aware
Configurable Computing in Nano-crossbar Fabric for Improved Yield”,
IEEE International On-Line Testing Symposium (IOLTS), pp.
29-36, 2007. [Abstract]
[Full
Text: PDF |
|
Swaroop Ghosh, Patrick N. Dai, Swarup Bhunia, and
Kaushik Roy, “Tolerance to Small Delay Defects by Adaptive Clock
Stretching”, IEEE International On-Line Testing Symposium (IOLTS),
pp. 244-252, 2007. [Abstract]
[Full
Text: PDF |
|
Seetharam Narasimhan,
Massood Tabib-Azar, Hillel J. Chiel, and Swarup Bhunia,
“Neural Data Compression with Wavelet Transform: A Vocabulary Based
Approach”, IEEE EMBS Conference on Neural Engineering, pp.
666-669, 2007. [Abstract]
[Full
Text: PDF |
|
Somnath Paul, Rajat Subhra Chakraborty,
and Swarup Bhunia, “VIm-Scan: A Low Overhead Scan Design Approach
for Protection of Secret Key in Scan-Based Secure Chips”, IEEE VLSI
Test Symposium (VTS), pp. 455-460, 2007 [Abstract]
[Full
Text: PDF ]. |
| Rajat Chakraborty, Seetharam Narasimhan, Swarup Bhunia, “Hybridization of CMOS with CNT-based Complementary Nano Electro-Mechanical Switch for Low-Leakage and Robust Embedded Memory Design”, Nanotech, pp. 134-137, 2007. [Abstract] |
|
Swarup Bhunia, Massood Tabib Azar, and
Daniel Saab, “Ultralow-Power Reconfigurable Computing with
Complementary Nano-Electromechanical Carbon Nanotube Switches”,
Asia
and South Pacific Design Automation Conference (ASP-DAC), pp. 86-91,
2007. [Abstract]
[Full
Text: PDF ] |
|
Siva Krishnamurthy, Somnath Paul, and
Swarup Bhunia,
“Adaptation to Temperature-Induced Delay Variations
in Logic Circuits Using Low-Overhead Online Delay Calibration”,
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on,
pp. 755-760, 2007.
[Abstract]
[Full Text: PDF ]
|
|
Swaroop Ghosh, Swarup Bhunia, and
Kaushik Roy, “Low-Overhead Circuit Synthesis for Temperature
Adaptation Using Dynamic Voltage Scheduling”, Design Automation and
Test in Europe (DATE), pp.1532-1537, 2007 [Abstract]
[Full
Text: PDF ]. |
| 2006 |
Swarup Bhunia, Massood Tabib Azar, and
Daniel Saab, “Ultralow-Power Adaptive System Architecture Using
Complementary Nano-Electromechanical Carbon Nanotube Switches,”
NANOARCH, Boston, MA, 2006. [Full
Text: PDF  ]. |
|
Massood Tabib-Azar, Swarup Bhunia, and
Daniel Saab, “Complimentary Nano-Electromechanical Carbon Nanotube
Switches,” Electrochem. Soc. 602, 2138, Cancun, Mexico, 2006. [Abstract]
[Full
Text: PDF ] |
|
Swaroop Ghosh, Swarup Bhunia, and
Kaushik Roy, “A New Paradigm for Low-power, Variation-Tolerant and
Adaptive Circuit Synthesis Using Critical Path Isolation”, IEEE
International Conference on Computer Aided Design (ICCAD), pp.
619-624, 2006. [Abstract]
[Full
Text: PDF ]. |
|
Ashish Goel, Swarup Bhunia, Hamid
Mahmoodi, and Kaushik Roy, “A Low-Overhead Design of
Soft-Error-Tolerant Scan Flip-Flop with Enhanced-Scan Capability”,
Asia and South Pacific Design Automation Conference (ASP-DAC), pp.
665-670, 2006. [Abstract] [Full Text: PDF ] |
|
Animesh Datta, Swarup Bhunia, Jung
Hwan Choi, Saibal Mukhopadhyay, and Kaushik Roy, “Speed Binning
Aware Design Methodology to Improve Profit under Parameter
Variations”, Asia and South Pacific Design Automation Conference
(ASP-DAC), pp. 712-717, 2006. [Best Paper Nominee][Abstract] [Full Text: PDF ] |
|
Nilanjan Banerjee, Swarup Bhunia,
Hamid Mahmoodi, and Kaushik Roy, “Low Power Synthesis of Dynamic
Logic Circuits Using Fine-Grained Clock Gating”, Design Automation
and Test in Europe (DATE), pp. 862-867, 2006. [Abstract] [Full Text: PDF ] |
|
Swaroop Ghosh, Swarup Bhunia, Arijit
Raychowdhury, Kaushik Roy, “Delay Fault Localization in
Test-Per-Scan BIST Using Built-In Delay Sensor”, pp. 31-36,
International On-Line Test Symposium (IOLTS), 2006. [Abstract] [Full Text: PDF ] |
|
Arijit Raychowdhury, Bipul Chandra
Paul, Swarup Bhunia, Kaushik Roy, “Ultralow power computing with
sub-threshold leakage: a comparative study of bulk and SOI
technologies”, Design and Test in Europe (DATE), 2006
[Abstract] [Full Text: PDF ] |
| 2005 |
|
Amit Agarwal, Kunhyuk Kang, Swarup
Bhunia, and Kaushik Roy, “Effectiveness of Low Power Dual-Vt Designs
in Nano-Scale Technologies under Process Parameter Variations”,
International Symposium on Low Power Electronics and Design (ISLPED),
pp. 14-19, 2005. [Abstract] [Full Text: PDF ] |
|
Swarup Bhunia, Hamid Mahmoodi,
Nilanjan Banerjee, Qikai Chen, and Kaushik Roy, “A Novel Synthesis
Approach for Active Leakage Power Reduction Using Supply Gating”,
Design Automation Conference (DAC), pp. 479-484, 2005. [Abstract] [Full Text: PDF ] |
|
Qikai Chen, Hamid Mahmoodi, Swarup Bhunia, and Kaushik Roy, “Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS”,
23rd IEEE VLSI Test Symposium (VTS), pp. 292-297, 2005. [Abstract] [Full Text: PDF ] |
|
Animesh Datta, Saibal Mukhopadhyay,
Swarup Bhunia, Kaushik Roy, “Yield Prediction of High Performance
Pipelined Circuit with Respect to Delay Failures in Sub-100nm
Technology”, International On-Line Test Symposium (IOLTS), 2005, pp.
275-280. [Abstract] [Full Text: PDF ] |
|
Animesh Datta, Swarup Bhunia, Saibal
Mukhopadhyay, Kaushik Roy, “A Statistical Approach to
Area-Constrained Yield Enhancement for Pipelined Circuits under
Parameter Variations”, Asian Test Symposium (ATS), 2005, pp.
170-175. [Abstract] [Full Text: PDF ] |
|
Swaroop Ghosh, Swarup Bhunia, Kaushik
Roy, “Shannon Expansion Based Supply-Gated Logic for Improved Power
and Testability”, Asian Test Symposium (ATS), pp. 404-409, 2005.
[Abstract] [Full Text: PDF ] |
|
Swarup Bhunia, Hamid Mahmoodi-Meimand,
Arijit Raychowdhury, Kaushik Roy, “A Novel Low-overhead Delay
Testing Technique for Arbitrary Two-Pattern Test Application”,
Design and Test in Europe (DATE), pp. 1136-1141, 2005. [Abstract] [Full Text: PDF ] |
|
Saibal Mukhopadhyay, Swarup Bhunia,
Kaushik Roy, “Modeling and Analysis of Loading Effect in Leakage of
Nano-Scaled Bulk-CMOS Logic Circuits”, Design and Test in Europe
(DATE), pp. 224-229, 2005. [Abstract] [Full Text: PDF ] |
|
Nilanjan Banerjee, Arijit Raychowdhury,
Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy, “Novel
Low-Overhead Operand Isolation Techniques for Low-Power Datapath
Synthesis”, International Conference on Computer Design (ICCD), pp.
1034-1039, 2005. [Abstract] [Full Text: PDF ] |
|
Animesh Datta, Swarup Bhunia, Nilanjan
Banerjee, Kaushik Roy, “A Power-Aware GALS Architecture for
Real-Time Algorithm-Specific Tasks”, International Symposium on
Quality Electronic Design (ISQED), pp. 358-363, 2005. [Abstract] [Full Text: PDF ] |
|
Swarup Bhunia, Hamid Mahmoodi-Meimand,
Debjyoti Ghosh, Kaushik Roy, “Power Reduction in Test-Per-Scan BIST
with Supply Gating and Efficient Scan Partitioning”, International
Symposium on Quality Electronic Design (ISQED), pp. 453-458, 2005.
[Abstract] [Full Text: PDF ] |
| 2004 |
|
Swarup Bhunia, Arijit Raychowdhury,
Kaushik Roy, “Frequency Specification Testing of Analog Filters
Using Wavelet Transform of Dynamic Supply Current”, International
Symposium on Quality Electronic Design (ISQED), pp. 243-255, 2004.
[Abstract] [Full Text: PDF ] |
|
Swarup Bhunia, Hamid Mahmoodi-Meimand,
Arijit Raychowdhury, Kaushik Roy, “First Level Hold: A Novel
Low-Overhead Delay Fault Testing Technique”, IEEE International
Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pp.
314-315, 2004. [Abstract] [Full Text: PDF ] |
|
Debjyoti Ghosh, Swarup Bhunia, Kaushik
Roy, “A Technique to Reduce Power and Test Application Time in BIST”,
International On-Line Test Symposium (IOLTS), pp. 182-184, 2004.
[Abstract] [Full Text: PDF ] |
|
Swarup Bhunia, Hamid Mahmoodi, Saibal
Mukhopadhyay, Debjyoti Ghosh, and Kaushik Roy, “A Novel Low Power
Scan Design Technique Using Supply Gating”, International Conference
on Computer Design (ICCD), pp. 60-65, 2004. [Best Paper Award]
[Abstract] [Full Text: PDF ] |
|
Swarup Bhunia, Arijit Raychowdhury,
Kaushik Roy, “Trim Bit Setting of Analog Filters Using Wavelet-Based
Supply Current Analysis”, Design Automation and Test in Europe
(DATE), 2004, pp. 10704-10709. [Abstract] [Full Text: PDF ] |
| 2003 and Earlier |
|
Swarup Bhunia and Kaushik Roy, “Defect
Oriented Testing of Analog Circuits Using Wavelet Analysis of
Dynamic Current”, Latin American Test Workshop (LATW), 2003. [Best
Paper Award]
[Abstract]
[Full Text: PDF ] |
|
Debjyoti Ghosh, Swarup Bhunia, and
Kaushik Roy, “Multiple Scan Chain Design Technique for Power
Reduction during Test Application in BIST”, IEEE International
Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pp.
191-196, 2003.
[Abstract]
[Full Text: PDF ] |
|
Hai Li, Swarup Bhunia, Yiran Chen,
Kaushik Roy, and T. N. Vijaykumar. “Deterministic Clock Gating for
Microprocessor Power Reduction”, International Symposium on
High-Performance Computing Architecture (HPCA), pp. 113-122, 2003.
[Abstract]
[Full Text: PDF ] |
|
Lih-yih Chiou, Swarup Bhunia, and
Kaushik Roy, “Synthesis of Application Specific Multi-Mode Systems”,
Design automation and Test In Europe (DATE), pp. 10096-10099, 2003.
[Abstract]
[Full Text: PDF ] |
|
Swarup Bhunia and Kaushik Roy, “Fault
Detection and Diagnosis Using Wavelet Based Transient Current
Analysis, Design Automation and Test in Europe (DATE), pp.
1118-1119, 2002.
[Abstract]
[Full Text: PDF ] |
|
Swarup Bhunia and Kaushik Roy,
“Dynamic Supply Current Testing of Analog Circuits Using Wavelet
Transform”, VLSI Test Symposium (VTS), pp. 302-307, 2002.
[Abstract]
[Full Text: PDF ] |
|
Swarup Bhunia and Kaushik Roy, “A
Novel Wavelet Transform Based Transient Current Analysis for Fault
Detection and Localization”, Design Automation Conference (DAC), pp.
361-366, 2002.
[Abstract]
[Full Text: PDF ] |
|
Swarup Bhunia, Hai Li, and Kaushik
Roy, “Gated-Ground Cache: A High Performance IDDQ-Testable Cache for
Scaled CMOS Technologies”, IEEE Asian Test Symposium (ATS), pp.
157-162, 2002.
[Abstract]
[Full Text: PDF ] |
|
Swarup Bhunia, Subhasish Majumdar,
Ayon Sirkar, and Susmita Sur-kolay, “Topological Routing amidst
Polygonal Obstacles”, 13th International VLSI Conference (VLSI
Design), pp. 274-279, 2000.
[Abstract]
[Full Text: PDF ] |
|
Swarup Bhunia, Soumya Ghosh, Pramod
Kumar, Partha Das, and Jayanta Mukherjee, “Design, Simulation and
Synthesis of an ASIC for Fractal Image Coding”, 12th International
VLSI Conference (VLSI Design), pp. 544-549, 1999.
[Abstract]
[Full Text: PDF ] |