INVITED CONFERENCE PUBLICATIONS

Published/Accepted for Publication

Disclaimer: The following publications are covered by copyright. Permission to make digital/hard copy of all or part of the following papers, technical reports, and presentations for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage. To copy otherwise, to republish, to post on servers, or to redistribute to lists requires prior specific permission.

Jonathan Cruz, Prabhat Mishra, and Swarup Bhunia, “The Metric Matters: The Art of Measuring Trust in Electronics", to appear in Design Automation Conference (DAC), Las Vegas, NV, USA, June 2019. [Special Session on “In CAD We Trust? The Question that Drives Trusted Microelectronics”]

Nagmeh Karimi, Jeyavijayan Rajendran, Hassan Salmani, Tamzidul Hoque, and Swarup Bhunia, “Countering IP Security threats in Supply chain", to appear in IEEE VLSI Test Symposium (VTS), Monterey, CA, USA, April 2019. [Special Session on Hardware IP Security]

Shuo Yang, Abdulrahman Alaql, Tamzidul Hoque, and Swarup Bhunia, “Runtime Integrity Verification in Cyber-physical Systems Using Side-Channel Fingerprint", IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, USA, Jan 2019.

Sarah Amir, Bicky Shakya, Domenic Forte, Mark Tehranipoor, and Swarup Bhunia, “Comparative Analysis of Hardware Obfuscation for IP Protection”, to appear in the 27th GLSVLSI, 2017. [Invited paper in special session on logic obfuscation]

Sandip Ray, Tamzidul Hoque, Abhishek Basak, and Swarup Bhunia, “The Power Play: Security-Energy Trade-offs in the IoT Regime”, 34th IEEE International Conference on Computer Design (ICCD), 2016. [Invited paper in special session on "Is security the Achilles heel of power-constrained SoCs?"]

Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, and Swarup Bhunia, “Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM”, 26th GLSVLSI, 2016.

Sandip Ray, Jin Yang, Abhishek Basak, and Swarup Bhunia, “Correctness and Security and Odds: Post-silicon Validation of Modern SoC Designs”, Design Automation Conference (DAC), 2015. [Invited paper in special session on system-on-chip security validation]

Robert Karam, Kai Yang, and Swarup Bhunia, “Energy-Efficient Reconfigurable Computing Using Spintronic Memory”, 58th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2015. [Invited paper in special session on Emerging Nanoelectronic Logic and Memory Devices based Circuits and Architectures]

Swarup Bhunia, Vaishnavi Ranganathan, Tina He, Srihari Rajgopal, Rui Wang, Mehran Mehregany and Philip Feng, “Toward Ultralow-Power Computing at Extreme with Silicon Carbide (SiC) Nanoelectromechanical Logic”, Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 1-6, 2014. [Abstract] [Full Text: PDF ]

Somnath Paul, Robert Karam, Swarup Bhunia, and Ruchir Puri, “Energy-Efficient Hardware Acceleration through Computing in the Memory”, DATE '14 Proceedings of the conference on Design, Automation & Test in Europe (DATE), 2014. [Abstract] [Full Text: PDF ]

Somnath Paul, Saibal Mukhopadhyay, and Swarup Bhunia, “Robust Low-Power Reconfigurable Computing with a Variation-Aware Preferential Design Approach”, IC Design & Technology (ICICDT), 2014 IEEE International Conference on, pp. 1-6, 2014. [Abstract] [Full Text: PDF ]

Abhishek Basak, Sanchita Mal-Sarkar, and Swarup Bhunia, “Secure and Trusted SoC: Challenges and Emerging Solutions”, 14th International Workshop on Microprocessor Test and Verification (MTV), 2013. [Invited paper in special session on Security test and verification] [Abstract] [Full Text: PDF ]

Abhishek Basak, Yu Zheng, Jangwon Park, Jongsun Park, and Swarup Bhunia, “Reconfigurable ECC for Adaptive Protection of Memory”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 4-7, 2013. [Invited paper in special session on Self-Healing and Self-adaptive RF/Mixed-signal circuits for low-cost, high-yield and robust systems] [Abstract] [Full Text: PDF ]

Xinmu Wang, Seetharam Narasimhan, Aswin Krishna, Tatini Mal-Sarkar, and Swarup Bhunia, “Sequential hardware Trojan: Side-channel aware design and placement”, 29th IEEE International Conference on Computer Design (ICCD), pp. 297-300, Oct 2011. [invited paper in the special session "Capture the Chip"] [Abstract] [Full Text: PDF ]

Srihari Rajgopal, Te-Hao Lee, Philip X.-L. Feng, Swarup Bhunia and Mehran Mehregany “Nano Manufacturing of SiC Circuits - Nanomechanical Logic and NEMS-JFET Integration”, Technologies for Future Micro-Nano Manufacturing Workshop, Aug 8-10, 2011. [Invited paper in special session] [Full Text: PDF ]

Hadi Hajimiri, Somnath Paul, Anandaroop Ghosh, Swarup Bhunia, and Prabhat Mishra, “Reliability Improvement in Many-Core Architectures through Computing in Embedded Memory”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, Aug 2011. [Invited paper in special session on self-healing circuits in scaled technologies] [Abstract] [Full Text: PDF ]

Seetharam Narasimhan, Jongsun Park, and Swarup Bhunia, “Digital Signal Processing in Bio-implantable Systems: Design Challenges and Emerging Solutions”, The Asia Symposium on Quality Electronic Design (ASQED), pp. 223-229, Aug 2010. [Invited paper in special session on bio-sensing and bio-system design] [Abstract] [Full Text: PDF ]

Swarup Bhunia and Anand Raghunathan, “Hardware Security: Design, Test and Validation Issues”, Hot topic Special Session in IEEE VLSI Test Symposium (VTS), pp. 349-349, 2010. [Invited one page article on the hot topic session] [Abstract] [Full Text: PDF ]

Rajat Subhra Chakraborty, Seetharam Narasimhan, and Swarup Bhunia, “Hardware Trojan: Threats and Emerging Solutions”, IEEE International High Level Design Validation and Test Workshop (HLDVT), pp. 166-171, 2009. [Invited paper in the special session on post-silicon validation] [Abstract] [Full Text: PDF ]

Somnath Paul and Swarup Bhunia, "Computing with Nanoscale Memory: Model and Architecture," IEEE/ACM International Symposium on Nanoscale Architecture (NANOARCH), pp. 1-6, 2009. [Invited paper in special session] [Abstract] [Full Text: PDF ]

Swarup Bhunia and Kaushik Roy, "Low Power Design under Parameter Variations", International Symposium on Low Power Electronics and Design (ISLPED), pp. 137, Aug 11-13, 2008. [One page article on embedded tutorial]  [Abstract] [FullText: PDF ]

Swarup Bhunia and Kaushik Roy, “Power Dissipation, Variations and Nanoscale CMOS Design: Test Challenges and Self Calibration/Self Repair Solutions”, International Test Conference (ITC), pp. 1-10, 2007. [Lecture series article] [Abstract] [Full Text: PDF ]

Swarup Bhunia, Saibal Mukhopadhyay, and Kaushik Roy, “Process Variations and Process-Tolerant Design”, International Conference on VLSI Design, pp. 699-704, 2007. [Abstract] [Full Text: PDF]