Adaptive Nanocomputing


Recent Publications on "Adaptive Nanocomputing"
Dongyeob Shin, Jangwon Park, Jongsun Park, Somnath Paul, and Swarup Bhunia, “Adaptive ECC for Tailored Protection of Nanoscale Memory”, IEEE Design & Test of Computers (D&T), to appear.
Robert Karam, Somnath Paul, Ruchir Puri, and Swarup Bhunia, “Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications”, ACM Journal of Emerging Technologies in Computing Systems (JETC), to appear.
Wenchao Qian, Chris Babecki, Robert Karam, Somnath Paul, and Swarup Bhunia, “ENFIRE: A Spatio-temporal Fine-grained Reconfigurable Hardware”, to appear in IEEE Transactions on VLSI Systems (TVLSI).
Robert Karam, Ruchir Puri, and Swarup Bhunia, “Energy-Efficient Adaptive Hardware Accelerator for Text Mining Application Kernels”, to appear in IEEE Transactions on VLSI Systems (TVLSI), 2016.
Christopher Babecki, Wenchao Qian, Somnath Paul, Robert Karam, and Swarup Bhunia, “A Memory-Centric Reconfigurable Hardware Accelerator for Security Applications”, IEEE Transactions on Computers (TComp), 2016, to appear.
Wenchao Qian, Christopher Babecki, Robert Karam, and Swarup Bhunia, “ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric”, 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2016, to appear.
Wenchao Qian, Pai-Yu Chen, Ligang Gao, Swarup Bhunia, and Shimeng Yu, “Energy-Efficient Adaptive Computing with Multifunctional Memory”, to appear in IEEE Transactions on Circuit and Systems-II (TCAS-II), 2016.
Robert Karam, Ruchir Puri, Swaroop Ghosh, and Swarup Bhunia, “Emerging Trends in Design and Applications of Memory based Computing and Content Addressable Memories”, Proceedings of the IEEE, to appear.
Wenbo Chen, Wenchao Lu, Branden Long, Yibo Li, David Gilmer, Gennadi Bersuker, Swarup Bhunia, and Rashmi Jha “Switching Characteristics of W/Zr/HfO2/TiN ReRAM Devices for Multi-level Cell Non-Volatile Memory Applications”, Semiconductor Science and Technology, IOP Publishing, to appear.
Kaushik Roy, Deliang Fan, Xuanyao Fong, Yusung Kim, Mrigank Sharad, Somnath Paul, Subho Chatterjee, Swarup Bhunia, and Saibal Mukhopadhyay, “Exploring Spin Transfer Torque Devices for Unconventional Computing”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), [Perspective paper in the Special issue on Computing in Emerging Technologies], vol. 5, no. 1, pp. 5-16, March 2015. [Abstract] [Full Text: PDF pdf]
Tina He, Fengchao Xhang, Swarup Bhunia, and Philip Feng “Silicon Carbide (SiC) Nanoelectromechanical Antifuse for Ultralow-Power FPGA Interconnects”, IEEE Journal of the Electron Devices Society (JEDS), to appear.
Robert Karam, Kai Yang, and Swarup Bhunia, “Energy-Efficient Reconfigurable Computing Using Spintronic Memory”, 58th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2015, to appear. [Invited paper in special session on Emerging Nanoelectronic Logic and Memory Devices based Circuits and Architectures]
Wen Yueh, Subho Chatterjee, Muneeb Zia, Student Member, Swarup Bhunia, and Saibal Mukhopadhyay, “A Memory-Based Logic Block with Optimized-for-Read SRAM for Energy-efficient Reconfigurable Computing Fabric”, to appear in IEEE Transactions on Circuits and Systems II (TCAS-II).
Somnath Paul, Aswin Krishna, Wenchao Qian, Robert Karam, and Swarup Bhunia, “MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. PP, no. 99, pp. 1, 2014. [Abstract] [ Full Text: PDF pdf]
Swarup Bhunia, Vaishnavi Ranganathan, Tina He, Srihari Rajgopal, Rui Wang, Mehran Mehregany and Philip Feng, “Toward Ultralow-Power Computing at Extreme with Silicon Carbide (SiC) Nanoelectromechanical Logic”, Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, pp. 1-6, 2014. [Abstract] [Full Text: PDF pdf]
Somnath Paul, Robert Karam, Swarup Bhunia, and Ruchir Puri, “Energy-Efficient Hardware Acceleration through Computing in the Memory”, DATE '14 Proceedings of the conference on Design, Automation & Test in Europe, 2014. [Abstract] [Full Text: PDF pdf]
Wenchao Qian, Robert Karam, and Swarup Bhunia, “Trade-off between Energy and Quality of Service Through Dynamic Operand Truncation and Fusion”, GLSVLSI '14 Proceedings of the 24th edition of the great lakes symposium on VLSI, pp. 79-81, 2014. [Abstract] [Full Text: PDF pdf]
Somnath Paul, Saibal Mukhopadhyay, and Swarup Bhunia, “Robust Low-Power Reconfigurable Computing with a Variation-Aware Preferential Design Approach”, IC Design & Technology (ICICDT), 2014 IEEE International Conference on, pp. 1-6, 2014. [Abstract] [Full Text: PDF pdf]
Vaishnavi Ranganathan, Tina He, Srihari Rajgopal, Mehran Mehregany, Philip X.-L. Feng, and Swarup Bhunia, “Analysis of Practical Scaling Limits in Nanoelectromechanical Switches”, The 9th Annual IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS), 2014.
Jongsun Park, Jangwon Park and Swarup Bhunia, “VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications”, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 61, no. 2, pp. 120-124, 2013. [Abstract] [ Full Text: PDF pdf]
Tina He, Vaishnavi Ranganathan, Rui Yang, Srihari Rajgopal, Mary Anne Tupta, Mehran Mehregany, Swarup Bhunia, and Philip X.-L. Feng, “Silicon Carbide (SiC) Nanoelectromechanical Switches and Logic Gates with Long Cycles and Robust Performance in Ambient Air and at High Temperature”, Micro Electro Mechanical Systems (MEMS), 2013 IEEE 26th International Conference on, pp. 516-519, 2013. [Abstract] [Full Text: PDF pdf]
Anandaroop Ghosh, Somnath Paul, Jongsun Park, and Swarup Bhunia, “Improving Energy Efficiency in FPGA through Judicious Mapping of Computation to Embedded Memory Blocks”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 22, no. 6, pp. 1314-1327, 2013. [Abstract] [ Full Text: PDF pdf]
Abhishek Basak, Yu Zheng, Jangwon Park, Jongsun Park, and Swarup Bhunia, “Reconfigurable ECC for Adaptive Protection of Memory”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 4-7, 2013. [Invited paper in special session on Self-Healing and Self-adaptive RF/Mixed-signal circuits for low-cost, high-yield and robust systems] [Abstract] [Full Text: PDF pdf]
Hadi Hajimiri, Prabhat Mishra, Swarup Bhunia, Branden Long, Yibo Li, and Rashmi Jha, “Content-aware Encoding for Improving Energy Efficiency in Resistive Random Access Memory”, Nanoscale Architectures (NANOARCH), 2013 IEEE/ACM International Symposium on, pp. 76-81, 2013. [Abstract] [Full Text: PDF pdf]
Vaishnavi Ranganathan, Tina He, Srihari Rajgopal, Mehran Mehregany, Philip X.-L. Feng, and Swarup Bhunia, “Robust Nanomechanical Non-Volatile Memory for Computing at Extreme”, Nanoscale Architectures (NANOARCH), 2013 IEEE/ACM International Symposium on, pp. 44-45, 2013. [Abstract] [Full Text: PDF pdf]
Tina He, Vaishnavi Ranganathan, Rui Yang, Srihari Rajgopal, Swarup Bhunia, Mehran Mehregany, and Philip X.-L. Feng, “Time-Domain AC Measurement of SiC Nanoelectromechanical Switches toward High Speed Operations”, Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS & EUROSENSORS XXVII), 2013 Transducers & Eurosensors XXVII: The 17th International Conference on, pp. 669-672, 2013. [Abstract] [Full Text: PDF pdf]
Tina He, Rui Yang, Srihari Rajgopal, Swarup Bhunia, Mehran Mehregany, and Philip X.-L. Feng, “Dual-gate silicon carbide (SiC) lateral nanoelectromechanical switches”, Nano/Micro Engineered and Molecular Systems (NEMS), 2013 8th IEEE International Conference on, pp. 554-557, 2013. [Best Student Paper Award] [Abstract] [Full Text: PDF pdf]
Tina He, Rui Yang, Srihari Rajgopal, Mary Anne Tupta, Swarup Bhunia, Mehran Mehregany, and Philip X.-L. Feng, “Robust Silicon Carbide (SiC) Nanoelectromechanical Switches with Long Cycles in Ambient and High Temperature Conditions”, Micro Electro Mechanical Systems (MEMS), 2013 IEEE 26th International Conference on, pp. 516-519, 2012. [Abstract] [Full Text: PDF pdf]
Hadi Hajimiri, Prabhat Mishra, and Swarup Bhunia, “Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures”, VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on, pp. 49-54, 2012. [Abstract] [Full Text: PDF pdf]
Kamran Rahmani, Prabhat Mishra, and Swarup Bhunia, “RMBC: Reconfigurable Memory-based Computing for Performance and Energy Improvement in Multicore Architectures”, GLSVLSI '12 Proceedings of the great lakes symposium on VLSI, pp. 287-290, 2012. [Abstract] [Full Text: PDF pdf]
Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay and Swarup Bhunia, “Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) Special Issue on Advances in Design of Energy-Efficient Circuits and Systems, vol. 1, no. 3, pp. 369-380, 2011. [Abstract] [Full Text: PDF pdf]
Srihari Rajgopal, Te-Hao Lee, Philip X.-L. Feng, Swarup Bhunia and Mehran Mehregany “Nano Manufacturing of SiC Circuits - Nanomechanical Logic and NEMS-JFET Integration”, Technologies for Future Micro-Nano Manufacturing Workshop, Aug 8-10, 2011. [Invited paper in special session] [Full Text: PDF pdf]
Hadi Hajimiri, Somnath Paul, Anandaroop Ghosh, Swarup Bhunia, and Prabhat Mishra, “Reliability Improvement in Many-Core Architectures through Computing in Embedded Memory”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, Aug 2011. [Invited paper in special session on self-healing circuits in scaled technologies] [Abstract] [Full Text: PDF pdf]
Xinmu Wang, Seetharam Narasimhan, and Swarup Bhunia, “NEMTronics: Symbiotic Integration of Nanoelectronic and Nanomechanical Devices for Energy-Efficient Adaptive Computing”, 7th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2011. [Abstract] [Full Text: PDF pdf]
Somnath Paul, Saibal Mukhopadhyay and Swarup Bhunia, “A variation-aware preferential design approach for memory based reconfigurable computing”, Proceedings of the 2009 International Conference on Computer-Aided Design, pp. 180-183, 2012. [Abstract] [ Full Text: PDF pdf]
Somnath Paul and Swarup Bhunia, “Memory Based Computing: Reshaping the fine-grained logic in a reconfigurable framework”, [Abstract] 18th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 283, 2011. [Abstract]
Xinmu Wang, Seetharam Narasimhan, Aswin Krishna, Francis G. Wolff, Srihari Rajgopal, Te-Hao Lee, Mehran Mehregany, and Swarup Bhunia, “High-Temperature (>500°C) FPGA Using SiC Nano-Electro-Mechanical System Switches”, Design Automation and Test in Europe (DATE), 2011. [Abstract] [Full Text: PDF pdf]

Keerthi Kunaparaju, Seetharam Narasimhan, and Swarup Bhunia, “VaROT: Variation-Tolerant DSP Circuits Using Post-Silicon Truncation of Operand Width”, IEEE International Conference on VLSI Design (VLSI), 2011. [Abstract] [Full Text: PDF pdf]

Somnath Paul and Swarup Bhunia, "Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 19, no. 8, pp. 1368-1379, 2011. [Abstract] [Full Text: PDF pdf]
Te-Hao Lee, Swarup Bhunia, and Mehran Mehregany, “Electromechanical Computing at 500°C with Silicon Carbide”, Science, vol. 329, no. 5997, pp. 1316-1318, Sep. 2010. [Abstract] [Full Text: PDF pdf]
Somnath Paul, Saibal Mukhopadhyay and Swarup Bhunia, "Circuit and Architecture Co-design Approach for Hybrid CMOS-STTRAM Non-volatile FPGA",  IEEE Transactions on Nanotechnology (TNANO), vol. 10, no. 3, pp. 385-394, 2010. [Abstract] [Full Text: PDF pdf]
Somnath Paul and Swarup Bhunia, "A Scalable Memory-based Reconfigurable Computing Framework for Nanoscale Crossbar", IEEE Transactions on Nanotechnology (TNANO), vol. pp, no. 99, pp. 1-10, 2010. [Abstract] [Full Text: PDF pdf]
Seetharam Narasimhan, Somnath Paul, Rajat Subhra Chakraborty, Francis Wolff, Christos Papachristou, Daniel Weyer, and Swarup Bhunia, "System Level Self-Healing for Parametric Yield and Reliability Improvement under Power Bound," NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2010. [Abstract] [Full Text: PDF pdf]
Chris Papachristou, Swarup Bhunia, and Francis Wolff, “Network Calibration of Embedded Sensors”, IEEE National Aerospace and Electronics Conference (NAECON), 2010. [Abstract] [Full Text: PDF pdf]
Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay and Swarup Bhunia, "A Circuit-Software Co-Design Approach for Improving EDP in Reconfigurable Frameworks," IEEE International Conference on Computer Aided Design (ICCAD), pp. 109-112, 2009. [Abstract] [Full Text: PDF pdf]
Somnath Paul, Saibal Mukhopadhyay and Swarup Bhunia, “A variation-aware preferential design approach for memory based reconfigurable computing”, Proceedings of the 2009 International Conference on Computer-Aided Design, pp. 180-183, 2012. [Abstract] [ Full Text: PDF pdf]
Somnath Paul and Swarup Bhunia, "Computing with Nanoscale Memory: Model and Architecture," IEEE/ACM International Symposium on Nanoscale Architecture (NANOARCH), pp. 1-6, 2009. [Invited paper in special session] [Abstract] [Full Text: PDF pdf]
Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay and Swarup Bhunia, “Nanoscale Reconfigurable Computing Using Non-Volatile 2-D STTRAM Array”, 9th International Conference on Nanotechnology (IEEE Nano), pp. 880-883, 2009. [Abstract] [Full Text: PDF pdf]

Te-Hao Lee, Kevin M. Speer, Xiaoan Fu, Swarup Bhunia, and Mehran Mehregany, "Polycrystalline Silicon Carbide NEMS for High-Temperature Logic," pp. 900-903, Transducers, 2009. [Abstract] [Full Text: PDF pdf]

Rajat Subhra Chakraborty, Somnath Paul, Yu Zhou and Swarup Bhunia, "Low-Power Hybrid CMOS-NEMS FPGA: Circuit Level Analysis and Defect-Aware Mapping",  IET Computers and Digital Techniques (IETCDT), vol. 3, no. 6, pp. 609-624, Nov. 2009. [Abstract] [ Full Text: PDF pdf]
Rajat Subhra Chakraborty, Seetharam Narasimhan, and Swarup Bhunia, "Hybridization of CMOS with CNT-Based Nano Electromechanical Switch for Low Leakage and Robust Circuit Design," IEEE Trans. on Circuits and Systems vol. 54, no. 7, pp. 2480-2488, Nov. 2007. [Abstract] [Full Text: PDF pdf]
Swaroop Ghosh, Swarup Bhunia, and Kaushik Roy, "CRISTA: A New Paradigm for Low-power, Variation-Tolerant and Adaptive Circuit Synthesis Using Critical Path Isolation," IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 26, no. 11, Nov. 2007. [Abstract] [Full Text: PDF pdf]

Te-Hao Lee, Kevin M. Speer, Kenji Okino, Xiaoan Fu, Swarup Bhunia, and Mehran Mehregany, “Polycrystalline-SiC Nanoelectromechanical Switches for High-Temperature Switching and Logic Applications”, IEEE Nanotechnology and Device Conference (NMDC), 2008. [Abstract] [Full Text: PDF pdf]

Somnath Paul, Saibal Mukhopadhyay, and Swarup Bhunia, “Hybrid CMOS-STTRAM FPGA Design Optimization for Low Power and High Integration Density”, IEEE International Conference on Computer Aided Design (ICCAD), pp. 589-592, 2008. [Abstract] [Full Text: PDF pdf]

Seetharam Narasimhan, Somnath Paul, and Swarup Bhunia, “Collective Computing Based on Swarm Intelligence”, Design Automation Conference (DAC), pp. 349-350, 2008. [as a WACI (Wild and Crazy Ideas) paper] [Abstract] [Full Text: PDF pdf]

Somnath Paul and Swarup Bhunia, “Reconfigurable Computing Using Content Addressable Memory for Improved Performance and Resource Usage”, Design Automation Conference (DAC), pp. 786-791, 2008. [Abstract] [Full Text: PDFpdf]

Rajat Subhra Chakraborty and Swarup Bhunia, “Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar”, IEEE International Symposium on Quality Electronic Design (ISQED), pp. 697-701, 2008. [Abstract] [Full Text: PDF pdf]

Rajat Subhra Chakraborty, Somnath Paul, and Swarup Bhunia, "Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits", International Conference on VLSI Design, pp. 441-446, 2008. [Abstract] [Full Text: PDF pdf]

Somnath Paul and Swarup Bhunia, "MBARC: A Scalable Memory Based Reconfigurable Computing Framework for Nanoscale Devices", Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 77-82, 2008. [Abstract] [Full Text: PDF pdf]

Seetharam Narasimhan, Yu Zhou, Hillel J. Chiel, and Swarup Bhunia, “Low-Power VLSI Architecture for Neural Data Compression Using Vocabulary-based Approach”, IEEE Biomedical Circuits and Systems Conference (BioCAS), 2007. [Abstract] [Full Text: PDF pdf]

Somnath Paul and Swarup Bhunia, “Memory Based Computation Using Embedded Cache for Processor Yield and Reliability Improvement”, International Conference on Computer Design (ICCD), pp. 341-346, 2007. [Abstract] [Full Text: PDF pdf]

Swarup Bhunia and Kaushik Roy, “Power Dissipation, Variations and Nanoscale CMOS Design: Test Challenges and Self Calibration/Self Repair Solutions”, International Test Conference (ITC), pp. 1-10, 2007. [Lecture series article] [Abstract] [Full Text: PDF pdf]

Somnath Paul, Siva Krishnamurthy, Hamid Mahmoodi, and Swarup Bhunia, “Low-Overhead Design Technique for Calibration of Maximum Frequency at Multiple Operating Points”, IEEE International Conference on Computer Aided Design (ICCAD), pp. 401-404, 2007. Abstract] [Full Text: PDF pdf]

Yu Zhou, Shijo Thekkel, and Swarup Bhunia, “Low power FPGA Design Using Hybrid CMOS-NEMS Approach”, International Symposium on Low Power Electronics and Design (ISLPED), pp. 14-19, 2007. [Abstract] [Full Text: PDF pdf]

Somnath Paul, Rajat Chakraborty, and Swarup Bhunia, “Defect-Aware Configurable Computing in Nano-crossbar Fabric for Improved Yield”, IEEE International On-Line Testing Symposium (IOLTS), pp. 29-36, 2007. [Abstract] [Full Text: PDF pdf]

Swaroop Ghosh, Patrick N. Dai, Swarup Bhunia, and Kaushik Roy, “Tolerance to Small Delay Defects by Adaptive Clock Stretching”, IEEE International On-Line Testing Symposium (IOLTS), pp. 244-252, 2007. [Abstract] [Full Text: PDF pdf]

Seetharam Narasimhan, Massood Tabib-Azar, Hillel J. Chiel, and Swarup Bhunia, “Neural Data Compression with Wavelet Transform: A Vocabulary Based Approach”, IEEE EMBS Conference on Neural Engineering, pp. 666-669, 2007. [Abstract] [Full Text: PDF pdf]

Swarup Bhunia, Massood Tabib Azar, and Daniel Saab, “Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches”, Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 86-91, 2007. [Abstract] [Full Text: PDF pdf]
Rajat Chakraborty, Seetharam Narasimhan, Swarup Bhunia, “Hybridization of CMOS with CNT-based Complementary Nano Electro-Mechanical Switch for Low-Leakage and Robust Embedded Memory Design”, Nanotech, pp. 134-137, 2007. [Abstract]
Siva Krishnamurthy, Somnath Paul, and Swarup Bhunia, "Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration", International Symposium on Quality Electronic Design (ISQED), 2007. [Abstract] [Full Text: PDF pdf]
Swarup Bhunia, Saibal Mukhopadhyay, and Kaushik Roy, “Process Variations and Process-Tolerant Design”, International Conference on VLSI Design, pp. 699-704, 2007. [Abstract] [Full Text: PDFpdf]
Somnath Paul, Rajat Subhra Chakraborty, and Swarup Bhunia, “VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips”, IEEE VLSI Test Symposium (VTS), pp. 455-460, 2007 [Abstract] [Full Text: PDF pdf].
Swaroop Ghosh, Swarup Bhunia, and Kaushik Roy, “Low-Overhead Circuit Synthesis for Temperature Adaptation Using Dynamic Voltage Scheduling”, Design Automation and Test in Europe (DATE), pp.1532-1537, 2007 [Abstract] [Full Text: PDF pdf].
Swarup Bhunia, Massood Tabib Azar, and Daniel Saab, “Ultralow-Power Adaptive System Architecture Using Complementary Nano-Electromechanical Carbon Nanotube Switches,” NANOARCH, Boston, MA, 2006. [Full Text: PDF pdf].
Swarup Bhunia, Massood Tabib Azar, and Daniel Saab, “Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches”, Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 86-91, 2007. [Abstract] [Full Text: PDF pdf]
Rajat Subhra Chakraborty and Swarup Bhunia, “A Study of Asynchronous Design Methodology for Robust CMOS-Nano Hybrid System Design”, ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 5, no. 3, pp. 12:1-12:22, Aug 2009. [Abstract] [ Full Text: PDF pdf]
Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, "CRISTA: A New Paradigm for Low-power, Variation-Tolerant and Adaptive Circuit Synthesis Using Critical Path Isolation", IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 26, no. 11, pp. 1947-1956, Nov. 2007. [Abstract] [Full Text: PDF pdf]