Low-Power and Robust VLSI Design

Recent Publications on "Low-Power and Robust VLSI Design"
Vaishnavi Ranganathan, Tina He, Srihari Rajgopal, Mehran Mehregany, Philip X.-L. Feng, and Swarup Bhunia, “Analysis of Practical Scaling Limits in Nanoelectromechanical Switches”, The 9th Annual IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS), 2014.
Abhishek Basak, Vaishnavi Ranganathan, and Swarup Bhunia, “A Wearable Ultrasonic Assembly for Point-Of-Care Autonomous Diagnostics of Malignant Growth”, Point-of-Care Healthcare Technologies (PHT), 2013 IEEE, pp. 128-131, 2013. [Best Student Paper Award] [Abstract] [Full Text: PDF pdf]
Seetharam Narasimhan, Keerthi Kunaparaju, and Swarup Bhunia, “Healing of DSP Circuits under Power Bound Using Post-Silicon Operand Bitwidth Truncation”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 9, pp. 1932-1941, 2012. [Abstract] [ Full Text: PDF pdf]
Anandaroop Ghosh, Somnath Paul, and Swarup Bhunia, “Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks”, VLSI Design (VLSID), 2012 25th International Conference on, pp. 424-429, 2011. [Abstract] [Full Text: PDF pdf]
Lei Wang, Somnath Paul, and Swarup Bhunia, “Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory”, 25th International Conference on VLSI Design (VLSI), pp. 340-345, 2012. [Best Paper Award] [Abstract] [Full Text: PDF pdf]
Abhishek Basak, Seetharam Narasimhan, and Swarup Bhunia, “KiMS: Kids' Health Monitoring System at Day-Care Centers using Wearable Sensors and Vocabulary-based Accoustic Signal Processing”, 13th IEEE International Conference on e-Health Networking, Application & Services (Healthcom), 2011. [Abstract] [Full Text: PDF pdf]

Seetharam Narasimhan, David McIntyre, Yu Zhou, Francis Wolff, Daniel Weyer, and Swarup Bhunia, “A Supply-Demand Model Based Scalable Energy Management System for Improved Energy Utilization Efficiency”, IEEE International Green Computing Conference (IGCC), 2010. [Abstract] [Full Text: PDF pdf]

Somnath Paul and Swarup Bhunia, “VAIL: Variation-Aware Issue Logic and Performance Binning for Processor Yield and Profit Improvement”,  International Symposium on Low Power Electronics and Design (ISLPED), 2010. [Abstract] [Full Text: PDF pdf]
Seetharam Narasimhan, Somnath Paul, Rajat Subhra Chakraborty, Francis Wolff, Christos Papachristou, Daniel Weyer, and Swarup Bhunia, "System Level Self-Healing for Parametric Yield and Reliability Improvement under Power Bound," NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2010. [Abstract] [Full Text: PDF pdf]
Somnath Paul, Hamid Mahmoodi and Swarup Bhunia, "Low-Overhead Fmax Calibration at Multiple Operating Points Using Delay Sensitivity Based Path Selection", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 15, no. 2, Feb. 2010. [Abstract] [ Full Text: PDF pdf]
Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, "Trifecta: A Non-Speculative Scheme to Exploit Common, Data-Dependent Subcritical Paths",  IEEE Trans. on Very Large Scale Integration Systems (TVLSI), vol. 18, no. 1, pp. 53-65, Jan. 2010. [Abstract] [Full Text: PDF pdf]
Patrick Ndai, Swarup Bhunia, Amit Agarwal and Kaushik Roy, "Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput", IEEE Transactions on Computers, vol. 57, no. 7, pp. 940-951, July 2008.[Abstract] [Full Text: PDF pdf]
Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, and Kaushik Roy, "Profit Aware Circuit Design under Process Variations Considering Speed Binning", IEEE Trans. on Very Large Scale Integration Systems, vol. 16, no. 7, pp. 806-815, July 2008. [Abstract] [Full Text: PDF pdf]
Swarup Bhunia and Kaushik Roy, "Low Power Design under Parameter Variations", International Symposium on Low Power Electronics and Design (ISLPED), pp. 137, Aug 11-13, 2008. [One page article on embedded tutorial]  [Abstract] [FullText: PDF pdf]

Yu Zhou, Somnath Paul, and Swarup Bhunia, “Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect”, IEEE International Symposium on Quality Electronic Design (ISQED), pp. 861-866, 2008. [Abstract] [Full Text: PDFpdf]

Lawrence Leinweber and Swarup Bhunia, “Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction”, Design Automation and Test in Europe (DATE), pp. 373-378, 2008. [Abstract] [Full Text: PDF pdf]

Yu Zhou, Somnath Paul and Swarup Bhunia, “Harvesting Wasted Heat in a Microprocessor Using Thermo-Electric Generators: Modeling, Analysis and Measurement”, Design Automation and Test in Europe (DATE), pp. 98-103, 2008. [Abstract] [Full Text: PDF pdf]

Matthew Holtz, Seetharam Narasimhan, and Swarup Bhunia, “On-die CMOS Voltage Droop Detection and Dynamic Compensation”, Great Lakes Symposium on VLSI (GLSVLSI), pp. 35-40, 2008. [Abstract] [Full Text: PDF pdf]
Swarup Bhunia and Kaushik Roy, “Power Dissipation, Variations and Nanoscale CMOS Design: Test Challenges and Self Calibration/Self Repair Solutions”, International Test Conference (ITC), pp. 1-10, 2007. [Lecture series article] [Abstract] [Full Text: PDF pdf]

Somnath Paul, Siva Krishnamurthy, Hamid Mahmoodi, and Swarup Bhunia, “Low-Overhead Design Technique for Calibration of Maximum Frequency at Multiple Operating Points”, IEEE International Conference on Computer Aided Design (ICCAD), pp. 401-404, 2007. Abstract] [Full Text: PDF pdf]

Swaroop Ghosh, Patrick N. Dai, Swarup Bhunia, and Kaushik Roy, “Tolerance to Small Delay Defects by Adaptive Clock Stretching”, IEEE International On-Line Testing Symposium (IOLTS), pp. 244-252, 2007. [Abstract] [Full Text: PDF pdf]
Siva Krishnamurthy, Somnath Paul, and Swarup Bhunia, “Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration”, Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on, pp. 755-760, 2007. [Abstract] [Full Text: PDF pdf]
Swarup Bhunia, Saibal Mukhopadhyay, and Kaushik Roy, “Process Variations and Process-Tolerant Design”, International Conference on VLSI Design, pp. 699-704, 2007. [Abstract] [Full Text: PDFpdf]