|Trojan Insertion Tool (TRIT)
|Nearly 1000 Trojan-inserted benchmark variants of ISCAS-85 and ISCAS-89 designs
generated using TRIT (more info). The combinational and sequential Trojans are available as TRIT-TC
and TRIT-TS, respectively
||A complete SoC benchmark written in Verilog with various IP blocks such as FFT,
DLX RISC uP, AES, and PMC. This example SoC design with the constituent IPs can be
used to evaluate and benchmark various security architectures and policies (more info).
for Security Training
|The HArdware HAcking boards are experimental development boards for teaching &
learning about hardware security.
The boards currently have the capacity to support a dozen
experiments that recreate different types of hardware security fundamentals, attacks,
countermeasures used in their defense.
|Security Accelerator or Co-Processor ISA
||The security accelerator or co-processor, is a specialized processor that is optimized to provide high performance and high energy-efficiency for diverse security applications (more info).
|Weighted Random Test
|Binary that generates weighted random a user specified number of
binary input vectors with a specified bit width.
More information on usage can be found in README.