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Tools & Benchmarks [Developed by Nanoscape Lab]
Disclaimer: All software, documents, and HDL files, etc., are provided as is. Academic, non-commercial users may use all provided files without charge for non-commercial purposes. The tools and benchmarks provided here cannot be used for commercial purposes. The developmnent of the tools and benchrmarks is funded in part by National Science Foundation (NSF).| Tool/Benchmark | Description | Download Link |
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| Trojan Insertion Tool (TRIT) Generated Benchmarks |
Nearly 1000 Trojan-inserted benchmark variants of ISCAS-85 and ISCAS-89 designs generated using TRIT (more info). The combinational and sequential Trojans are available as TRIT-TC and TRIT-TS, respectively |
TRIT-TC.zip TRIT-TS.zip |
| SoC Benchmark | A complete SoC benchmark written in Verilog with various IP blocks such as FFT, DLX RISC uP, AES, and PMC. This example SoC design with the constituent IPs can be used to evaluate and benchmark various security architectures and policies (more info). |
README SoC_Model.zip |
| HAHA Board for Security Training |
The HArdware HAcking boards are experimental development boards for teaching & learning about hardware security. The boards currently have the capacity to support a dozen experiments that recreate different types of hardware security fundamentals, attacks, and countermeasures used in their defense. |
Design_Files.zip Testing_Manual.pdf |
| Security Accelerator or Co-Processor ISA | The security accelerator or co-processor, is a specialized processor that is optimized to provide high performance and high energy-efficiency for diverse security applications (more info). | MAHA_ISA.pdf InstructionEncodings.xlsx |
| Weighted Random Test Generation Tool |
Binary that generates weighted random a user specified number of binary input vectors with a specified bit width. More information on usage can be found in README. |
README testGen |