FULL-DAY / HALF-DAY TUTORIALS

Full-Day Tutorials
Patrick Schaumont, Swarup Bhunia, Kazuo Sakiyama, and Makoto Nagata, “Hardware Trust in VLSI Design and Implementations” 20th Asia South Pacific Design Automation Conference (ASPDAC), 2015. Organizer: Kazuo Sakiyama, UEC and Makoto Nagata, Kobe University. [Full-Day Tutorial]
Srivaths Ravi, Anand Ragunathan, Eric Peeters, and Swarup Bhunia, “Designing Secure SoCs” 26th IEEE International Conference on VLSI Design (VLSI), 2013. Organizer: Srivaths Ravi, Texas Instruments. [Full-Day Tutorial]
Susmita Sur-Kolay and Swarup Bhunia, “Intellectual Property Protection and Security in System on a Chip” 25th IEEE International Conference on VLSI Design (VLSI), 2012. Organizer: Susmita Sur-Kolay, Indian Statistical Institute. [Full-Day Tutorial]
Rahul Rao, Saibal Mukhopadhyay, Swarup Bhunia, and Praveen Elakkumanan, “Parameter Variations and Low-Power Design: Test Issues and On-chip Calibration/Repair Solutions” International Test Conference (ITC), 2010. Organizer: Rahul Rao, IBM Research. [Full-Day Tutorial]
Rahul Rao, Praveen Elakkumanan, Saibal Mukhopadhyay and Swarup Bhunia,“Parametric Failures and Self-Calibration/Self-Repair Solutions”, in International Test Conference (ITC), 2009. Organizer: Saibal Mukhopadhyay, Georgia Tech. [Full-Day Tutorial]
Saibal Mukhopadhyay, Rahul Rao, Praveen Elakkumanan, and Swarup Bhunia, “Parametric Failures and Self-Calibration/Self-Repair Solutions in Nanometer Technologies”, in IEEE International On-Line Test Symposium (IOLTS), 2009. Organizer: Saibal Mukhopadhayay, Georgia Tech. [Full-Day Tutorial]
Half-Day & Embedded Tutorials
Swarup Bhunia, “Hardware Security in the IoT Regime: New Frontiers” IEEE Custom Integrated Circuits Conference (CICC), April 14-17, 2019. Organizer: Arijit Raychowdhury, Georgia Tech. [Half-Day Tutorial]
Sandip Ray and Swarup Bhunia, “System-on-Chip Platform Security: Architecture, Implementation, Validation, and Deployment” 11th Hardware Oriented Security and Trust (HOST), April 30, 2018. Organizer: Sandip Ray, University of Florida. [Half-Day Tutorial]
Domenic Forte and Swarup Bhunia, “Test Opportunities and Challenges for Secure Hardware and Verifying Trust in Integrated Circuits”, International Test Conference (ITC), Fort Worth, Texas, Nov 15-17, 2016, Organizer: Domenic Forte (U. of Florida). [Half-Day Tutorial]
Swarup Bhunia, “SECURITY - What are the interactions of hardware faults with system security?” IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, USA, April, 2016. [Embedded Tutorial]
Swaroop Ghosh, Jaydeep Kulkarni, and Swarup Bhunia, “Embedded Memory Design for Future Technologies: Challenges, Solutions and Applications”, upcoming in Design Automation and Test in Europe (DATE) Conference, 2015. Organizer: Swaroop Ghosh, U. of South Florida. [Half-Day Tutorial]
Swarup Bhunia, “Secure and Trustworthy System-on-Chip: Threats and Protections”, upcoming in 16th International Symposium on Quality Electronic Design (ISQED), 2015. Organizer: Arijit Raychowdhury, Georgia Tech. [Embedded Tutorial]
Prabhat Mishra, Swarup Bhunia and Srivaths Ravi, “Validation and Debug of Security and Trust Issues in Embedded Systems”, upcoming in 28th IEEE International Conference on VLSI Design (VLSI), 2015. Organizer: Prabhat Mishra, U. of Florida. [Half-Day Tutorial]
Swarup Bhunia, Kanak B. Agarwal and Kaushik Roy, “Low Power Design under Parameter Variations”, in Design Automation and Test in Europe (DATE) Conference, 2009. Organizer: Swarup Bhunia, Case Western Reserve U. [Half-Day Tutorial]
Swarup Bhunia, “Variation-Tolerant Low-Power Logic Circuit”, in International Symposium on Quality Electronic Design (ISQED), 2009. Organizer: Rajiv Joshi, IBM Research. [Embedded Tutorial]
Swarup Bhunia and Kaushik Roy, “Low Power Design under Parameter Variations”, in IEEE International SOC Conference (SOCC), 2008. Organizer: Swarup Bhunia, Case Western Reserve U. [Half-Day Tutorial]
Kaushik Roy and Swarup Bhunia, “Low Power Design under Parameter Variations”, in International Symposium on Low Power Electronics and Design (ISLPED), 2008. Organizer: Swarup Bhunia, Case Western Reserve U. [Embedded Tutorial]
Swarup Bhunia and Kaushik Roy, “Process Variations and Process-Tolerant Design”, in International Conference on VLSI Design, 2007. Organizer: Swarup Bhunia, Case Western Reserve U. [Embedded Tutorial]